The AZ10/100LVEL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple LVEL32’s in a system. The LVEL32 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the.
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• Operating Range of 3.0V to 5.5V 470ps Propagation Delay 3.0GHz Toggle Frequency High Bandwidth Output Transitions Direct Replacement for ON Semiconductor MC10EL/LVEL32 & MC100EL/LVEL32 PACKAGE
SOIC 8 Green / RoHS Compliant / Lead (Pb) Free TSSOP 8 Green / RoHS Compliant / Lead (Pb) Free MLP 8 (2x2) Green / RoHS Compliant / Lead (Pb) Free
1 2 3
ECL/PECL ÷ 2 Divider
PACKAGE AVAILABILITY PART NUMBER
AZ100LVEL32DG AZ100LVEL32TG AZ100LVEL32NG
MARKING
AZM100G LVEL32 AZHG LV32 C2G
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | AZ100LVEL33 |
Arizona Microtek |
ECL/PECL / 4 Divider | |
2 | AZ100LVEL11 |
Arizona Microtek |
ECL/PECL 1:2 Differential Fanout Buffer | |
3 | AZ100LVEL16 |
Arizona Microtek |
ECL/PECL Differential Receiver | |
4 | AZ100LVEL16VR |
ETC |
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | |
5 | AZ100LVEL16VRL |
ETC |
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | |
6 | AZ100LVEL16VRLR1 |
ETC |
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | |
7 | AZ100LVEL16VRLR2 |
ETC |
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | |
8 | AZ100LVEL16VRX |
ETC |
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | |
9 | AZ100LVEL16VS |
Arizona Microtek |
ECL/PECL Differential Receiver | |
10 | AZ100LVEL16VT |
Arizona Microtek |
ECL/PECL Oscillator Gain Stage & Buffer | |
11 | AZ100LVEL16VV |
Arizona Microtek |
Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer | |
12 | AZ100LVEL58 |
Arizona Microtek |
ECL/PECL 2:1 Multiplexer |