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The ASM5I9774A is a low-voltage high-performance 125MHz PLL-based zero delay buffer designed for highspeed clock distribution applications. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Block Diagram VCO_SEL PLL_E.
Output frequency range: 8.3MHz to 125MHz Input frequency range: 4.2MHz to 62.5MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 14 Clock outputs: Drive up to 28 clock lines 2 LVCMOS reference clock inputs 150 pS max output-output skew PLL bypass mode ‘SpreadTrak’ Output enable/disable Pin compatible with MPC9774 and CY29774AI. Industrial temperature range:
–40°C to +85°C 52Pin 1.0mm TQFP package RoHS Compliance
ASM5I9774A
The ASM5I9774A features two reference clock inputs and provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide .
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | ASM5I9772A |
Alliance Semiconductor |
12-Output Zero Delay Buffer |
|
| 2 | ASM5I9773A |
Alliance Semiconductor |
12-Output Zero Delay Buffer |
|
| 3 | ASM5I9775A |
Alliance Semiconductor |
14-Output Zero Delay Buffer |
|
| 4 | ASM5I9350 |
Alliance Semiconductor |
3.3V 1:10 LVCMOS PLL Clock Generator |
|
| 5 | ASM5I9351 |
Alliance Semiconductor |
9-Output Zero Delay Buffer |
|
| 6 | ASM5I9352 |
Alliance Semiconductor |
11-Output Zero Delay Buffer |
|
| 7 | ASM5I961C |
Alliance Semiconductor |
Low Voltage Zero Delay Buffer |
|
| 8 | ASM5I961P |
Alliance Semiconductor |
Low Voltage Zero Delay Buffer |
|
| 9 | ASM5I9653A |
Alliance Semiconductor |
3.3V 1:8 LVCMOS PLL Clock Generator |
|
| 10 | ASM5I9658 |
Alliance Semiconductor |
3.3V 1:10 LVCMOS PLL Clock Generator |
|
| 11 | ASM5I2304A |
Alliance Semiconductor |
3.3 V Zero Delay Buffer |
|
| 12 | ASM5I2304B |
Alliance Semiconductor |
3.3 V Zero Delay Buffer |
|