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The ASM5I9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the ASM5I9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selec.
1:8 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply ASM5I9653A running at either 4x or 8x of the reference clock frequency. The ASM5I9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25MHz. The ASM5I9653A has a differential LVPECL reference input long with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | ASM5I9658 |
Alliance Semiconductor |
3.3V 1:10 LVCMOS PLL Clock Generator |
|
| 2 | ASM5I961C |
Alliance Semiconductor |
Low Voltage Zero Delay Buffer |
|
| 3 | ASM5I961P |
Alliance Semiconductor |
Low Voltage Zero Delay Buffer |
|
| 4 | ASM5I9350 |
Alliance Semiconductor |
3.3V 1:10 LVCMOS PLL Clock Generator |
|
| 5 | ASM5I9351 |
Alliance Semiconductor |
9-Output Zero Delay Buffer |
|
| 6 | ASM5I9352 |
Alliance Semiconductor |
11-Output Zero Delay Buffer |
|
| 7 | ASM5I9772A |
Alliance Semiconductor |
12-Output Zero Delay Buffer |
|
| 8 | ASM5I9773A |
Alliance Semiconductor |
12-Output Zero Delay Buffer |
|
| 9 | ASM5I9774A |
Alliance Semiconductor |
12-Output Zero Delay Buffer |
|
| 10 | ASM5I9775A |
Alliance Semiconductor |
14-Output Zero Delay Buffer |
|
| 11 | ASM5I2304A |
Alliance Semiconductor |
3.3 V Zero Delay Buffer |
|
| 12 | ASM5I2304B |
Alliance Semiconductor |
3.3 V Zero Delay Buffer |
|