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The ASM5I9352 is a low voltage high performance 200MHz PLL-based zero delay buffer designed for high speed clock distribution applications. When PLL_EN# is HIGH, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Alliance Semiconductor 2575.
Output frequency range: 25MHz to 200MHz Output frequency range: 16.67MHz to 200MHz Input frequency range: 16.67MHz to 200MHz ASM5I9352 The ASM5I9352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series te.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | ASM5I9350 |
Alliance Semiconductor |
3.3V 1:10 LVCMOS PLL Clock Generator |
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| 2 | ASM5I9351 |
Alliance Semiconductor |
9-Output Zero Delay Buffer |
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| 3 | ASM5I961C |
Alliance Semiconductor |
Low Voltage Zero Delay Buffer |
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| 4 | ASM5I961P |
Alliance Semiconductor |
Low Voltage Zero Delay Buffer |
|
| 5 | ASM5I9653A |
Alliance Semiconductor |
3.3V 1:8 LVCMOS PLL Clock Generator |
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| 6 | ASM5I9658 |
Alliance Semiconductor |
3.3V 1:10 LVCMOS PLL Clock Generator |
|
| 7 | ASM5I9772A |
Alliance Semiconductor |
12-Output Zero Delay Buffer |
|
| 8 | ASM5I9773A |
Alliance Semiconductor |
12-Output Zero Delay Buffer |
|
| 9 | ASM5I9774A |
Alliance Semiconductor |
12-Output Zero Delay Buffer |
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| 10 | ASM5I9775A |
Alliance Semiconductor |
14-Output Zero Delay Buffer |
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| 11 | ASM5I2304A |
Alliance Semiconductor |
3.3 V Zero Delay Buffer |
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| 12 | ASM5I2304B |
Alliance Semiconductor |
3.3 V Zero Delay Buffer |
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