Pin CK, CK CKE CS ODT RAS, CAS, WE DM (DMU), (DML) Type Input Input Input Input Input Input Function Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK Clock Enable : CKE HIGH ac.
- Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; center-aligned with data for WRITEs - Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS - Data mask (DM) for write data - Posted CAS by.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | AS4C256M16D3LB-12BCN |
Alliance Semiconductor |
4Gb DRAM | |
2 | AS4C256M16D3LB-12BIN |
Alliance Semiconductor |
4Gb DRAM | |
3 | AS4C256M16D3L |
Alliance Semiconductor |
256M x 16 bit DDR3L Synchronous DRAM | |
4 | AS4C256M16D3LA-12BIN |
Alliance Semiconductor |
256M x 16 bit DDR3L Synchronous DRAM | |
5 | AS4C256M16D3A-12BIN |
Alliance Semiconductor |
256M x 16 bit DDR3 Synchronous DRAM | |
6 | AS4C256M16D3B-12BCN |
Alliance Semiconductor |
Double-data-rate architecture | |
7 | AS4C256K16E0 |
Alliance Semiconductor |
5V 256K x 16 CMOS DRAM | |
8 | AS4C256K16FO |
Alliance Semiconductor |
5V 256K x 16 CMOS DRAM | |
9 | AS4C2GM4D3L |
Alliance Semiconductor |
DDR3L SDRAM | |
10 | AS4C2M32S |
Alliance Semiconductor |
2M x 32 bit Synchronous DRAM | |
11 | AS4C2M32SA-6TCN |
Alliance Semiconductor |
64Mb SDRAM | |
12 | AS4C2M32SA-6TIN |
Alliance Semiconductor |
64Mb SDRAM |