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AS4C256M16D3LB-12BAN |
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| Part Number | AS4C256M16D3LB-12BAN |
| Manufacturer | Alliance Semiconductor |
| Description | Pin CK, CK CKE CS ODT RAS, CAS, WE DM (DMU), (DML) Type Input Input Input Input Input Input Function Clock : CK and CK are differential clock inputs. All address and control input signals are sampl... |
| Features |
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver
- DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
- Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
- Data mask (DM) for write data - Posted CAS by... |
| Document |
 AS4C256M16D3LB-12BAN Data Sheet
PDF 1.88MB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | AS4C256M16D3LB-12BCN |
Alliance Semiconductor |
4Gb DRAM |
|
| 2 | AS4C256M16D3LB-12BIN |
Alliance Semiconductor |
4Gb DRAM |
|
| 3 | AS4C256M16D3L |
Alliance Semiconductor |
256M x 16 bit DDR3L Synchronous DRAM |
|
| 4 | AS4C256M16D3LA-12BIN |
Alliance Semiconductor |
256M x 16 bit DDR3L Synchronous DRAM |
|
| 5 | AS4C256M16D3A-12BIN |
Alliance Semiconductor |
256M x 16 bit DDR3 Synchronous DRAM |
|