The 9DBL06 devices are 3.3V members of IDT's Full-Featured PCIe family. The 9DBL06 supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL06P1 can be factory programmed with a user-define.
• 6
– 1-200 MHz Low-Power (LP) HCSL DIF pairs
• 9DBL0641 default ZOUT = 100
• 9DBL0651 default ZOUT = 85
• 9DBL06P1 factory programmable defaults
Key Specifications
• PCIe Gen1-2-3-4 CC compliant in ZDB mode
• PCIe Gen2 SRIS compliant in ZDB mode
• Supports PCIe Gen2-3 SRIS in fan-out mode
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew < 50ps
• Byp.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 9DBL02 |
IDT |
2-output 3.3V PCIe Zero-Delay Buffer | |
2 | 9DBL0242 |
Renesas |
Zero-Delay/Fanout Buffer | |
3 | 9DBL0242 |
IDT |
2-output 3.3V PCIe Zero-Delay Buffer | |
4 | 9DBL0242C |
Renesas |
2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers | |
5 | 9DBL0243 |
IDT |
2-Output 3.3V LP-HCSL Zero-Delay Buffer | |
6 | 9DBL0252 |
Renesas |
Zero-Delay/Fanout Buffer | |
7 | 9DBL0252 |
IDT |
2-output 3.3V PCIe Zero-Delay Buffer | |
8 | 9DBL0252C |
Renesas |
2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers | |
9 | 9DBL0253 |
IDT |
2-Output 3.3V LP-HCSL Zero-Delay Buffer | |
10 | 9DBL0255 |
Renesas |
2 and 4-Output 3.3V PCIe Gen1-5 Clock Fanout Buffers | |
11 | 9DBL0255 |
IDT |
PCIe Gen1-5 Clock Fanout Buffers | |
12 | 9DBL04 |
IDT |
4-output 3.3V PCIe Zero-delay Buffer |