The 74LVC3G17-Q100 is a triple buffer with Schmitt-trigger inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potenti.
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low-power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standards
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection: .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LVC3G17 |
NXP |
Triple non-inverting Schmitt trigger | |
2 | 74LVC3G17 |
nexperia |
Triple non-inverting Schmitt trigger | |
3 | 74LVC3G14 |
NXP |
Triple inverting Schmitt trigger | |
4 | 74LVC3G14 |
nexperia |
Triple inverting Schmitt trigger | |
5 | 74LVC3G16 |
nexperia |
Triple buffer | |
6 | 74LVC3G04 |
NXP |
Triple inverter | |
7 | 74LVC3G04 |
DIODES |
TRIPLE INVERTER GATE | |
8 | 74LVC3G04 |
nexperia |
Triple inverter | |
9 | 74LVC3G04-Q100 |
nexperia |
Triple inverter | |
10 | 74LVC3G06 |
NXP Semiconductors |
Triple inverter | |
11 | 74LVC3G06 |
nexperia |
Triple inverter | |
12 | 74LVC3G07 |
NXP Semiconductors |
Triple buffer |