The 74LVC3G16 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G16 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current throug.
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant input/output for interfacing with 5 V logic
• High noise immunity
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LVC3G14 |
NXP |
Triple inverting Schmitt trigger | |
2 | 74LVC3G14 |
nexperia |
Triple inverting Schmitt trigger | |
3 | 74LVC3G17 |
NXP |
Triple non-inverting Schmitt trigger | |
4 | 74LVC3G17 |
nexperia |
Triple non-inverting Schmitt trigger | |
5 | 74LVC3G17-Q100 |
nexperia |
Triple non-inverting Schmitt trigger | |
6 | 74LVC3G04 |
NXP |
Triple inverter | |
7 | 74LVC3G04 |
DIODES |
TRIPLE INVERTER GATE | |
8 | 74LVC3G04 |
nexperia |
Triple inverter | |
9 | 74LVC3G04-Q100 |
nexperia |
Triple inverter | |
10 | 74LVC3G06 |
NXP Semiconductors |
Triple inverter | |
11 | 74LVC3G06 |
nexperia |
Triple inverter | |
12 | 74LVC3G07 |
NXP Semiconductors |
Triple buffer |