SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS WITH ADDRESS LATCHES DATA OUTPUTS VCC 16 Y0 15 Y0 A B C GL G2 G1 Y1 14 Y1 Y2 13 Y2 Y3 12 Y3 Y4 11 Y4 Y5 10 Y5 Y6 Y7 16 1 LOW POWER SCHOTTKY Y6 9 J SUFFIX CERAMIC CASE 620-09 1 A 2 B SELECT 3 C 4 GL 5 G2 ENABLE 6 G1 7 8 Y7 GND OUTPUT.
H L H X Y0 H H L H H H H H H H Y1 H H H L H H H H H H Y2 H H H H L H H H H H Y3 H H H H H L H H H H Y4 H H H H H H L H H H Y5 H H H H H H H L H H Y6 H H H H H H H H L H Y7 H H H H H H H H H L Output corresponding to stored address, L; all others, H H = high level, L = low level, X = irrelevant (1) A (15) Y0 (14) Y1 (13) SELECT INPUTS (2) B (12) Y3 DATA (11) (3) C (10) Y5 Y4 OUTPUTS Y2 (9) (4) GL (7) (5) G2 (6) G1 Y7 Y6 ENABLE INPUTS FAST AND LS TTL DATA 5-226 SN54/74LS137 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH P.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LS13 |
Motorola |
SCHMITT TRIGGERS DUAL GATE/HEX INVERTER | |
2 | 74LS13 |
Fairchild Semiconductor |
Dual 4-Input Schmitt Trigger | |
3 | 74LS13 |
Raytheon |
NAND Gates | |
4 | 74LS132 |
ON Semiconductor |
LOW POWER SCHOTTKY | |
5 | 74LS132 |
Fairchild Semiconductor |
Quad 2-Input NAND Gate | |
6 | 74LS132 |
Hitachi Semiconductor |
Quadruple 2-input Positive NAND Schmitt-triggers | |
7 | 74LS132 |
Motorola |
QUAD 2-INPUT SCHMITT TRIGGER NAND GATE | |
8 | 74LS133 |
Motorola |
13-INPUT NAND GATE | |
9 | 74LS134 |
ETC |
12-input NAND gate | |
10 | 74LS136 |
Fairchild Semiconductor |
Quad 2-Input Exclusive-OR Gate | |
11 | 74LS136 |
Hitachi Semiconductor |
Quadruple 2-input Exclusive-OR Gates | |
12 | 74LS138 |
Fairchild Semiconductor |
Decoder/Demultiplexer |