The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the m.
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• Input levels:
• For 74HC107-Q100: CMOS level
• For 74HCT107-Q100: TTL level
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 p.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74HCT107 |
Philips |
Dual JK flip-flop | |
2 | 74HCT107 |
nexperia |
Dual JK flip-flop | |
3 | 74HCT107D |
nexperia |
Dual JK flip-flop | |
4 | 74HCT10 |
Philips |
Triple 3-input NAND gate | |
5 | 74HCT10 |
nexperia |
Triple 3-input NAND gate | |
6 | 74HCT10-Q100 |
nexperia |
Triple 3-input NAND gate | |
7 | 74HCT109 |
nexperia |
Dual JK flip-flop | |
8 | 74HCT109 |
Philips |
Dual JK flip-flop | |
9 | 74HCT109-Q100 |
nexperia |
Dual JK flip-flop | |
10 | 74HCT109D |
nexperia |
Dual JK flip-flop | |
11 | 74HCT10D |
nexperia |
Triple 3-input NAND gate | |
12 | 74HCT10DB |
nexperia |
Triple 3-input NAND gate |