74HC/HCT10 The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determi.
• Output capability: standard
• ICC category: SSI GENERAL DESCRIPTION
74HC/HCT10
The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fO) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load ca.
The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting r.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74HCT10-Q100 |
nexperia |
Triple 3-input NAND gate | |
2 | 74HCT107 |
Philips |
Dual JK flip-flop | |
3 | 74HCT107 |
nexperia |
Dual JK flip-flop | |
4 | 74HCT107-Q100 |
nexperia |
Dual JK flip-flop | |
5 | 74HCT107D |
nexperia |
Dual JK flip-flop | |
6 | 74HCT109 |
nexperia |
Dual JK flip-flop | |
7 | 74HCT109 |
Philips |
Dual JK flip-flop | |
8 | 74HCT109-Q100 |
nexperia |
Dual JK flip-flop | |
9 | 74HCT109D |
nexperia |
Dual JK flip-flop | |
10 | 74HCT10D |
nexperia |
Triple 3-input NAND gate | |
11 | 74HCT10DB |
nexperia |
Triple 3-input NAND gate | |
12 | 74HCT10PW |
nexperia |
Triple 3-input NAND gate |