The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the .
s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s Asynchronous common reset s True and complement output Ordering Code: Order Number 74F175SC 74F175SJ 74F175PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram © 199.
The ’F175 is a high-speed quad D flip-flop The device is useful for general flip-flop requirements where clock and clear.
This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (C.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74F173 |
NXP |
Quad D-type flip-flop 3-State | |
2 | 74F174 |
NXP |
Hex D flip-flops | |
3 | 74F174 |
Fairchild Semiconductor |
Hex D-Type Flip-Flop with Master Reset | |
4 | 74F174 |
National Semiconductor |
Hex D Flip-Flop with Master Reset | |
5 | 74F175A |
NXP |
Quad D flip-flop | |
6 | 74F1763 |
NXP |
Intelligent DRAM controller | |
7 | 74F1779 |
Philips |
8-bit bidirectional binary counter | |
8 | 74F10 |
NXP |
Triple 3-input NAND gate | |
9 | 74F10 |
Fairchild Semiconductor |
Triple 3-Input NAND Gate | |
10 | 74F10 |
National Semiconductor |
Triple 3-Input NAND Gate | |
11 | 74F10 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATE | |
12 | 74F1056 |
Fairchild Semiconductor |
8-Bit Schottky Barrier Diode Array |