The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the correspondin.
• Six edge-triggered D-type flip-flops
• Buffered common Clock
• Buffered, asynchronous Master Reset
DESCRIPTION
The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. All Q outputs will be forced Low independent of Clock or Data inputs by a Low voltage level on the MR .
The 74F174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register.
The ’F174 is a high-speed hex D flip-flop The device is used primarily as a 6-bit edge-triggered storage register The in.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74F173 |
NXP |
Quad D-type flip-flop 3-State | |
2 | 74F175 |
Texas Instruments |
Quad D-Type Flip-Flop | |
3 | 74F175 |
Fairchild Semiconductor |
Quad D-Type Flip-Flop | |
4 | 74F175 |
National Semiconductor |
Quad D Flip-Flop | |
5 | 74F175A |
NXP |
Quad D flip-flop | |
6 | 74F1763 |
NXP |
Intelligent DRAM controller | |
7 | 74F1779 |
Philips |
8-bit bidirectional binary counter | |
8 | 74F10 |
NXP |
Triple 3-input NAND gate | |
9 | 74F10 |
Fairchild Semiconductor |
Triple 3-Input NAND Gate | |
10 | 74F10 |
National Semiconductor |
Triple 3-Input NAND Gate | |
11 | 74F10 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATE | |
12 | 74F1056 |
Fairchild Semiconductor |
8-Bit Schottky Barrier Diode Array |