The 74F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress negative transients caused by line reflections, switching noise and crosstalk. Features s 8-Bit array structure designed to suppress negative transients s Guaranteed ESD protection .
s 8-Bit array structure designed to suppress negative transients s Guaranteed ESD protection (HBM) in excess of 4 kV s Common anode shared by all eight diodes s Broadside pinout for ease of bus routing Ordering Code: Order Number 74F1056SC Package Number M16A Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Schematic Diagram © 1999 Fairchild Semiconductor Corporation DS011655 www.fairchildsemi.com 74F1056 Absolute M.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74F10 |
NXP |
Triple 3-input NAND gate | |
2 | 74F10 |
Fairchild Semiconductor |
Triple 3-Input NAND Gate | |
3 | 74F10 |
National Semiconductor |
Triple 3-Input NAND Gate | |
4 | 74F10 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATE | |
5 | 74F1071 |
Fairchild Semiconductor |
18-Bit Undershoot/Overshoot Clamp | |
6 | 74F109 |
National Semiconductor |
Dual JK Positive Edge-Triggered Flip-Flop | |
7 | 74F109 |
NXP |
Positive J-K positive edge-triggered flip-flops | |
8 | 74F109 |
Fairchild Semiconductor |
Dual JK Positive Edge-Triggered Flip-Flop | |
9 | 74F109 |
Texas Instruments |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP | |
10 | 74F11 |
National Semiconductor |
Triple 3-Input AND Gate | |
11 | 74F11 |
Fairchild Semiconductor |
Triple 3-Input AND Gate | |
12 | 74F11 |
NXP |
Triple 3-input NAND gate |