The 74AUP1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption acros.
s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E Class 3A exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides pa.
The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable ap.
The 74AUP1G07 is a single buffer with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74AUP1G00 |
NXP Semiconductors |
Low-power 2-input NAND gate | |
2 | 74AUP1G00 |
Diodes |
SINGLE 2 INPUT POSITIVE NAND GATE | |
3 | 74AUP1G00 |
nexperia |
Low-power 2-input NAND gate | |
4 | 74AUP1G00-Q100 |
nexperia |
Low-power 2-input NAND gate | |
5 | 74AUP1G02 |
NXP |
Low-power 2-input NOR gate | |
6 | 74AUP1G02 |
Diodes |
SINGLE 2 INPUT POSITIVE NOR GATE | |
7 | 74AUP1G02 |
nexperia |
Low-power 2-input NOR gate | |
8 | 74AUP1G02-Q100 |
nexperia |
Low-power 2-input NOR gate | |
9 | 74AUP1G04 |
NXP Semiconductors |
Low-power inverter | |
10 | 74AUP1G04 |
STMicroelectronics |
Low power single inverter gate | |
11 | 74AUP1G04 |
Diodes |
SINGLE INVERTER GATE | |
12 | 74AUP1G04 |
nexperia |
Low-power inverter |