The 74AUP1G02-Q100 is a single 2-input NOR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuit.
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 0.8 V to 3.6 V
• CMOS low power dissipation
• High noise immunity
• Overvoltage tolerant inputs to 3.6 V
• Low noise overshoot and undershoot < 10 % of VCC
• IOFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Low static power consumption; ICC = 0.9 μA (maximum)
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.9 V to 1.65 V)
• JESD8-7 (1..
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74AUP1G02 |
NXP |
Low-power 2-input NOR gate | |
2 | 74AUP1G02 |
Diodes |
SINGLE 2 INPUT POSITIVE NOR GATE | |
3 | 74AUP1G02 |
nexperia |
Low-power 2-input NOR gate | |
4 | 74AUP1G00 |
NXP Semiconductors |
Low-power 2-input NAND gate | |
5 | 74AUP1G00 |
Diodes |
SINGLE 2 INPUT POSITIVE NAND GATE | |
6 | 74AUP1G00 |
nexperia |
Low-power 2-input NAND gate | |
7 | 74AUP1G00-Q100 |
nexperia |
Low-power 2-input NAND gate | |
8 | 74AUP1G04 |
NXP Semiconductors |
Low-power inverter | |
9 | 74AUP1G04 |
STMicroelectronics |
Low power single inverter gate | |
10 | 74AUP1G04 |
Diodes |
SINGLE INVERTER GATE | |
11 | 74AUP1G04 |
nexperia |
Low-power inverter | |
12 | 74AUP1G04-Q100 |
nexperia |
Low-power inverter |