The LS192 and LS193 are Asynchronously Presettable Decade and 4-Bit Binary Synchronous UP / DOWN (Reversable) Counters. The operating modes of the LS192 decade counter and the LS193 binary counter are identical, with the only difference being the count sequences as noted in the State Diagrams. Each circuit contains four master/slave flip-flops, with internal.
y Internally Provided
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
V CC
P0
16
15
MR TC D TC U PL
14
13 12 11
P2
P3
10
9
1
2
3
4
5
6
7
8
P1
Q1
Q 0 CP D CP U Q 2
Q 3 GND
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
CPU CPD MR
Count Up Clock Pulse Input Count Down Clock Pulse Input Asynchronous Master Reset (Clear) Input
0.5 U.L. 0.5 U.L. 0.5 U.L.
0.25 U.L. 0.25 U.L. 0.25 U.L.
PL
Asynchronous Parallel Load (Active LOW) Input 0.5 .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 54LS190 |
Texas Instruments |
SYNCHRONOUS UP/DOWN COUNTERS | |
2 | 54LS190 |
Motorola |
PRESETTABLE BCD/DECADE UP/DOWN COUNTERS | |
3 | 54LS190 |
National Semiconductor |
Synchronous 4-Bit Up/Down Counters | |
4 | 54LS191 |
Motorola |
PRESETTABLE BCD/DECADE UP/DOWN COUNTERS | |
5 | 54LS191 |
Texas Instruments |
SYNCHRONOUS UP/DOWN COUNTERS | |
6 | 54LS192 |
Motorola |
PRESETTABLE BCD/DECADE UP/DOWN COUNTER | |
7 | 54LS10 |
National Semiconductor |
Triple 3-Input NAND Gates | |
8 | 54LS109 |
National Semiconductor |
Dual Positive-Edge-Triggered J-K Flip-Flops | |
9 | 54LS109A |
Texas Instruments |
Dual J-K Positive-Edge-Triggered Flip-Flops | |
10 | 54LS11 |
National Semiconductor |
Triple 3-Input AND Gates | |
11 | 54LS114 |
National Semiconductor |
Dual JK Flip-Flop | |
12 | 54LS122 |
Texas Instruments |
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS |