| No. | Partie # | Fabricant | Description | Fiche Technique |
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Zarlink Semiconductor |
CMOS Gate Arrays • • • • • • • • • • • 0.35µm drawn Channel Length Three (CLT) and Four (CLQ) layer metal options Automated base array constructor for optimised arrays with up to 3 million gates Low Power, 0.4µ W/MHz/Gate at 3V (2-input NAND with two loads) 135ps gat |
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Zarlink Semiconductor |
Channel Less CMOS Gate Arrays have been incorporated such as analog functionality, slew rate output control, and intermediate I/O buffering for optimum data transfer through peripheral cells. Also, the low-power characteristics of Zarlink Semiconductor CMOS processing have been i |
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Zarlink Semiconductor |
High Density CMOS Gate Arrays • • • • Low power channelless arrays from 5,000 to 250,000 available gates (5µ W / gate / MHz) 1 micron (0.8 micron effective) twin well epitaxial process Typical gate delays of 400 ps (NAND2 , Fanout=2) Comprehensive cell library including DSP, JTAG |
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Zarlink Semiconductor |
High Density CMOS Gate Arrays I I I I I I I I I I 0.7µ (0.8µ drawn) process Typical gate delay 210ps Accurate simulation delay (multi platform support) Support for industry standard workstations Comprehensive cell library 3V option for low power operation Split rail operation (op |
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Zarlink Semiconductor |
High Density CMOS Gate Arrays I Low power, 0.5µW/MHz/gate at 3V supply (NAND 2 loads) I High density of 5,425 available gates/mm2 I 3V and 5V I/O capability on the same device I 150ps gate delay for 2-input NAND with two loads (5V) I Accurate delay modelling for gates and tracks |
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