| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
ST Microelectronics |
N-CHANNEL Power MOSFET Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s H |
|
|
|
|
STMicroelectronics |
Serial Flash Memory SUMMARY s 4 Mbit of Flash Memory s Page Program (up to 256 Bytes) in 1.5ms (typical) s Sector Erase (512 Kbit) in 2 s (typical) s Bulk Erase (4 Mbit) in 5 s (typical) s 2.7 V to 3.6 V Single Supply Voltage s SPI Bus Compatible Serial Interface s 25 M |
|
|
|
|
ST Microelectronics |
M25P40 SUMMARY s 4 Mbit of Flash Memory s Figure 1. Packages Page Program (up to 256 Bytes) in 1.5ms (typical) Sector Erase (512 Kbit) in 2 s (typical) (4 Mbit) in 5 s (typical) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Interface 25 M |
|
|
|
|
STMicroelectronics |
N-CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR or VISO Insulation Withstand Voltage (DC) Tstg Storage Temperature Tj Max. Operating Junction Temperature ( •) Pulse width limited by safe operating area July 1993 Val ue STP40N10 ST P4 0N 10 F I 100 100 ± 20 40 22 28 15 160 160 150 |
|
|
|
|
STMicroelectronics |
Thermal Data |
|
|
|
|
STMicroelectronics |
STP40NF10L uos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 100 100 ± 17 40 25 160 150 1 4 |
|
|
|
|
STMicroelectronics |
N-Channel MOSFET SIZE™ ” POWER MOSFET TYPE ST P40NE03L-20 s s s s V DSS 30 V R DS(on) <0.020 Ω ID 40 A TYPICAL RDS(on) = 0.014 Ω EXCEPTIONAL dv/dt CAPABILITY LOW GATE CHARGE A 100 oC APPLICATION ORIENTED CHARACTERIZATION 1 2 3 DESCRIPTION This Power MOSFET is th |
|
|
|
|
STMicroelectronics |
STP40NF10 RATINGS Symbol VDS VDGR VGS ID(*) ID IDM (l) PTOT dv/dt (1) EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100° |
|
|
|
|
STMicroelectronics |
DisplayPort transmitter ■ Enhanced DisplayPort® (DP) transmitter – DP 1.1a compliant – Embedded DisplayPort (eDP) compliant – 1, 2, or 4 lanes ■ Higher bandwidth “Turbo mode” (3.24 Gbps) per lane, supports: – 1920 x 1080 (FHD) 120 Hz/10-bit color video standard timings and |
|
|
|
|
STMicroelectronics |
4 Mbit/ Low Voltage/ Serial Flash Memory SUMMARY s 4 Mbit of Flash Memory s Figure 1. Packages Page Program (up to 256 Bytes) in 1.5ms (typical) Sector Erase (512 Kbit) in 2 s (typical) Bulk Erase (4 Mbit) in 5 s (typical) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Int |
|
|
|
|
ST Microelectronics |
N-CHANNEL POWER MOSFET ain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 100 100 ± 15 40 25 160 150 1 430 –65 to 175 175 Un |
|
|
|
|
STMicroelectronics |
32-bit MCU ■ Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h) – Compliant with Power Architecture® embedded category – Variable Length Encoding (VLE) ■ Memory organization – Up to 256 KB on-chip code flash memory with ECC and erase/program controll |
|
|
|
|
STMicroelectronics |
N-CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR or VISO Insulation Withstand Voltage (DC) Tstg Storage Temperature Tj Max. Operating Junction Temperature ( •) Pulse width limited by safe operating area July 1993 Val ue STP40N10 ST P4 0N 10 F I 100 100 ± 20 40 22 28 15 160 160 150 |
|
|
|
|
STMicroelectronics |
N-CHANNEL MOSFET TYPE www.DataSheet4U.com STP40N20 Figure 1: Package ID 40 A 40 A 40 A Pw 160 W 160 W 160 W 3 1 2 1 2 3 VDSS 200 V 200 V 200 V RDS(on) < 0.045 Ω < 0.045 Ω < 0.045 Ω STW40N20 STB40N20 ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.038 Ω GATE CHARGE MINIMIZED VE |
|
|
|
|
STMicroelectronics |
N-channel Power MOSFET Order code STP40NF10 VDSS 100 V RDS(on) max. < 0.028 Ω ID 50 A ■ Exceptional dv/dt capability ■ Low gate charge ■ 100% avalanche tested Application Switching applications Description This N-channel 100 V Power MOSFET is the latest development |
|
|
|
|
STMicroelectronics |
DisplayPort receiver ■ Enhanced DisplayPort® (DP) receiver – DP 1.1a compliant – Embedded DisplayPort (eDP) compliant – 1, 2, or 4 lanes ■ Higher bandwidth “Turbo mode” (3.24 Gbps per lane), supports: – 1920 x 1080 (FHD) 120 Hz/10-bit color video standard timings and 7.1 |
|
|
|
|
STMicroelectronics |
MEDIUM POWER AMPLIFIER Max Max 62.5 8 o o C/W C/W • Mounted on a ceramic substrate area = 30 x 35 x 0.7 mm ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) Symbol I CBO V (BR)CBO Parameter Collector Cut-off Current (I E = 0) Collector-Base Breakdow |
|
|
|
|
STMicroelectronics |
Low gate charge STripFET Power MOSFET Type STB40N20 STP40N20 STP40N20FP STW40N20 ■ ■ ■ ■ ■ VDSS 200V 200V 200V 200V RDS(on) <0.045Ω <0.045Ω <0.045Ω <0.045Ω ID 40A 40A 40A 40A PW 160W 160W 160W 40W TO-220 1 2 3 3 1 D2PAK Gate charge minimized Very low intrinsic capacitances Very g |
|
|
|
|
ST Microelectronics |
N-Channel MOSFET 0 90 0.6 6 -65 to 175 175 Unit V V V A A A W W/ C V/ns o o o C C ( •) Pulse width limited by safe operating area March 1996 1/7 STP40N03L-20 THERMAL DATA R t hj-ca se R t hj- amb R thc- si nk Tl Thermal Resistance Junction-case Thermal Resistan |
|
|
|
|
ST Microelectronics |
N-CHANNEL POWER MOSFET Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s H |
|