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Synchronous Decade Counter an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes coincident with each other when so instructed by the count-enab |
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1-of-8-line Data Selector/Multiplexer both true (Y) and complement (W) outputs. The strobe input must be at a low logic level to enable this multiplexer. A high logic level at the strobe forces the W output high and the Y output low. Features • High Speed Operation: tpd (Any D to Y or |
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12-bit Address Comparator and enable input (G). When G is low, the device is enabled. When G is high, the device is disabled and the output is high regardless of the A and P inputs. Features • High Speed Operation: tpd (A to Y) = 18 ns typ (CL = 50 p |
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Quadruple 2-Input Positive NOR Gates • Ordering Information REJ03D0389 –0200 Rev.2.00 Feb.18.2005 Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS02P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS02FPEL SOP-14 pin (JEITA) PRSP0014DF-B FP (FP-14DA |
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Renesas |
Octal Bus Transceivers low power dissipation that is about 1/5 of high speed bipolar logic IC. When the frequency is 10 MHz. The device has eight bus transceivers with three state outputs in a 20 pin package. Each device has an active low enable input (G) and a direction c |
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Renesas |
Hex Inverters / Hex Inverters • Ordering Information • HD74LS04 Part Name HD74LS04P HD74LS04FPEL HD74LS04RPEL Package Type DILP-14 pin SOP-14 pin (JEITA) SOP-14 pin (JEDEC) Package Code (Previous Code) PRDP0014AB-B (DP-14AV) PRSP0014DF-B (FP-14DAV) PRSP0014DE-A (FP-14DNV) Pac |
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Renesas |
Dual Retriggerable Monostable Multivibrators output pulse width control by three method. The basic pulse time is programmed by selection of external resistance and capacitance values. Once triggered, the basic pulse width may be extended by retriggering the gated low-level -active (A) or high-l |
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Renesas Technology |
Retriggerable Monostable Multivibrator output pulse duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A input is low, the B input is high, and t |
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18-bit Universal Bus Transceivers • VCC = 2.3 V to 3.6 V • Typical VOL ground bounc |
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Dual JK Negative Edge-Triggered Flip-Flop individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will p |
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Renesas |
16-bit Buffers / Line Drivers • VCC = 2.7 to 5.5 V • All inputs VIH (Max) = 5.5 V (@VCC = 0 to 5.5 V) • All outputs VO (Max) = 5.5 V (@VCC = 0 V or output off state) • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, |
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Renesas |
Dual Bus Buffer Inverted • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • Supply voltage range : 1.2 to 3.6 V Operating temperature range: −40 to +85°C • All inputs VIH (Max.) = 3.6 V (@V |
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Renesas |
Octal D-type Transparent Latches • High Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C |
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Renesas |
Dual Retriggerable Monostable Multivibrators output pulse width control by three method. The basic pulse time is programmed by selection of external resistance and capacitance values. Once triggered, the basic pulse width may be extended by retriggering the gated low-level -active (A) or high-l |
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Renesas |
Quadruple 2-Input Positive AND Gates • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS08P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS08FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP HD74LS08RPEL SOP-14 pin (JEDEC) PR |
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Renesas |
8-Bit Parallel-Out Serial-in Shift Register gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip-flop to the low level at the ne |
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Renesas |
Octal Bus Transceivers • High Speed Operation: tpd = 12 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) • Order |
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Renesas |
8-bit Shift Register gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift / load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock |
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Renesas |
Quadruple 2-Input Positive AND Gates • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS08P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS08FPEL SOP-14 pin (JEITA) PRSP0014DF-B FP (FP-14DAV) HD74LS08RPEL SOP-14 pin (JEDEC) |
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Renesas |
Octal D-type Flip-Flops • High Speed Operation: tpd (S to Q) = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C |
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