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HD74ACT112 |
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| Part Number | HD74ACT112 |
| Manufacturer | Renesas (https://www.renesas.com/) |
| Description | The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic l... |
| Features |
individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.
Features
• Outputs Source/Sink 24 mA • HD74ACT112 has TTL-Compatible Inputs • Ordering Information: Ex. HD74AC112 Part Name Package Type Package Code Package Abbreviation Tapi... |
| Document |
 HD74ACT112 Data Sheet
PDF 209.33KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | HD74ACT112 |
Hitachi Semiconductor |
Dual JK Negative Edge-Triggered Flip-Flop |
|
| 2 | HD74ACT107 |
Hitachi Semiconductor |
Dual JK Flip-Flop (with Separate Clear and Clock) |
|
| 3 | HD74ACT107 |
Renesas |
Dual JK Flip-Flop |
|
| 4 | HD74ACT125 |
Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output |
|
| 5 | HD74ACT125 |
Renesas |
Quad Buffer/Line Driver |
|