| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
NXP |
QorIQ integrated communication processor • Two e5500 Power Architecture cores (one on the P5010) – Each core has a backside 512-Kbyte L2 Cache with ECC – Three levels of instructions: User, Supervisor, and Hypervisor – Independent boot and reset – Secure boot capability • CoreNet fabric su |
|
|
|
|
NXP |
QorIQ integrated communication processor • Two e5500 Power Architecture cores (one on the P5010) – Each core has a backside 512-Kbyte L2 Cache with ECC – Three levels of instructions: User, Supervisor, and Hypervisor – Independent boot and reset – Secure boot capability • CoreNet fabric su |
|
|
|
|
NXP |
Silicon PIN diode and benefits • Two elements in common cathode configuration in a small-sized plastic SMD package • Low diode capacitance • Low diode forward resistance 1.3 Applications • General RF application 2 Pinning information Table 1. Discrete pinning Pin De |
|
|
|
|
NXP |
Silicon PIN diode and benefits • Two elements in common cathode configuration in a small-sized plastic SMD package • Low diode capacitance • Low diode forward resistance 1.3 Applications • General RF applications 2 Pinning information Table 1. Discrete pinning Pin |
|
|
|
|
NXP |
TrenchMOS transistor Standard level FET very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in DC-DC converters and general purpose switching applications. PHP50N03T QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETE |
|
|
|
|
NXP |
General purpose PIN diode and benefits • Low diode capacitance • Low diode forward resistance 1.3 Applications • General RF application NXP Semiconductors BAP50-03 Silicon PIN diode 2 Pinning information Table 1. Discrete pinning Pin Description 1 cathode 2 anode Sim |
|
|
|
|
NXP |
Silicon PIN diode and benefits • Two elements in series configuration in a small-sized plastic SMD package • Low diode capacitance • Low diode forward resistance 1.3 Applications • General RF application NXP Semiconductors BAP50-04 Silicon PIN diode 2 Pinning infor |
|
|
|
|
NXP |
General purpose PIN diode and benefits • Low diode capacitance • Low diode forward resistance 1.3 Applications • General RF applications NXP Semiconductors BAP50-02 General purpose PIN diode 2 Pinning information Table 1. Discrete pinning Pin Description 1 cathode 2 a |
|
|
|
|
NXP |
Silicon PIN diode |
|
|
|
|
NXP |
High voltage USB PD power switch and benefits Wide supply voltage range from 2.5 V to 20 V ISW maximum 5 A continuous current 29 V tolerance on both VBUS and VINT pin 30 m (typical) Low ON resistance Adjustable VBUS over voltage protection Built in slew rate control for |
|
|
|
|
NXP |
N-channel TrenchMOS transistor Logic level FET • ’Trench’ technology • Very low on-state resistance • Fast switching • High thermal cycling performance • Low thermal resistance • Logic level compatible PHP50N03LT, PHB50N03LT PHD50N03LT QUICK REFERENCE DATA d SYMBOL VDSS = 25 V ID = 48 A RDS(ON |
|
|
|
|
NXP |
TrenchMOS transistor Logic level FET • ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance PHP50N06LT, PHB50N06LT, PHD50N06LT SYMBOL d QUICK REFERENCE DATA VDSS = 55 V ID = |
|
|
|
|
NXP |
NPN Darlington transistors • High current (max. 1 A) • Low voltage (max. 80 V) • Integrated diode and resistor. APPLICATIONS • Industrial high gain amplification. PINNING PIN 1 2,4 3 BSP50; BSP51; BSP52 DESCRIPTION base collector emitter 4 2, 4 DESCRIPTION NPN Darlington t |
|
|
|
|
NXP |
General purpose PIN diode • Two elements in series configuration in a small SMD plastic package • Low diode capacitance • Low diode forward resistance. APPLICATIONS • General RF applications. DESCRIPTION Two planar PIN diodes in series configuration in an SOT323 small SMD pla |
|
|
|
|
NXP Semiconductors |
PHP50N03LT • ’Trench’ technology • Very low on-state resistance • Fast switching • High thermal cycling performance www.DataSheet4U.com • Low thermal resistance • Logic level compatible PHP50N03LT, PHB50N03LT PHD50N03LT QUICK REFERENCE DATA d SYMBOL VDSS = 2 |
|
|
|
|
NXP |
PowerMOS transistor rage temperature Junction temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 60 60 30 52 36 208 150 175 175 UNIT V V V A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resist |
|