No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
|
|
NXP |
4-bit up/down decade counter ly. The outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum count state of ‘9’, the next HIGH to LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW |
|
|
|
NXP |
HEX inverting buffers and benefits Accepts input voltages in excess of the supply voltage Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard |
|
|
|
NXP |
Dual D-type flip-flop independent set direct (SD), clear direct (CD), clock inputs (CP) and outputs (O, O). Data is accepted when CP is LOW and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct |
|
|
|
NXP |
Programmable 4-bit binary down counter and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering in |
|
|
|
NXP |
4-bit synchronous decade counter |
|
|
|
NXP |
Quadruple static decade counters allows common busing of the outputs. The counters are supplied with asynchronous reset and preset to 19 999 facilities making them suitable for counter and time base applications. All carry signals are available except from the first decade. Schmitt- |
|
|
|
NXP |
24-stage frequency divider and oscillator tly the HEF4521B will count up to 224 = 16777216. The counting advances on the HIGH to LOW transition of the clock (I2). The outputs of the last seven stages are available for additional flexibility. Fig.1 Functional diagram. FAMILY DATA, IDD LIMIT |
|
|
|
NXP |
Quadruple 2-input NOR gate and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B Inputs and outputs are protected against el |
|
|
|
NXP |
Quadruple 2-input NAND gate Quadruple 2-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On Output transition times HIGH to LOW 5 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPHL; tPLH SYMBOL T |
|
|
|
NXP |
4-bit universal shift register 195B MSI input. When PE is LOW, data are loaded into the register from P0 to P3 on the LOW to HIGH transition of CP. When PE is HIGH, data are shifted into the first register position from J and K and all the data in the register are shifted one posi |
|
|
|
NXP |
Dual 4-channel analogue multiplexer/demultiplexer and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications Analog |
|
|
|
NXP |
4-wide 2-input AND-OR-invert gate SO; plastic (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. PINNING I0 to I8 I9 O gate inputs gate input (active LOW) output (active LOW) FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 |
|
|
|
NXP |
Dual 4-bit latch dance OFF-state regardless of other input conditions. This allows the outputs to interface directly with bus orientated systems. When EO is LOW the contents of the latches are available at the outputs. Fig.1 Functional diagram. FAMILY DATA, IDD LIM |
|
|
|
NXP |
Dual binary counter (O0 to O3 = LOW) independent of CP0, CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.2 Pinning diagram. HEF4520BP(N): HEF4520BD(F): HEF4520BT(D): 16-lead DIL; plastic (SOT3 |
|
|
|
NXP |
Dual monostable multivibrator and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering in |
|
|
|
NXP |
Dual precision monostable multivibrator • Separate reset inputs • Triggering from leading or trailing edge • ICC category: MSI DESCRIPTION The HEF4938B is a dual retriggerable-resettable monostable multivibrator. Each multivibrator has an active LOW trigger/retrigger input (I0), an active |
|
|
|
NXP |
4-bit bidirectional universal shift register llel operation are edge-triggered on the LOW to HIGH transition of CP. The inputs at which the data are to be entered and S0, S1 must be stable for a set-up time before the LOW to HIGH transition of CP. Fig.2 Pinning diagram. HEF40194BP(N): 16-lead |
|
|
|
NXP |
Octal bus transceiver with 3-state outputs output stages with high current output capability suitable for driving highly capacitive loads. The direction input (DR) controls transmission of data from bus A to bus B, or bus B to bus A, depending on its logic level. The 3-state outputs are contr |
|
|
|
NXP |
12-stage binary counter set input (active HIGH) parallel outputs APPLICATION INFORMATION Some examples of applications for the HEF4040B are: • Frequency dividing circuits • Time delay circuits Fig.2 Pinning diagram. • Control counters FAMILY DATA, IDD LIMITS category MSI H |
|
|
|
NXP |
Monostable/astable multivibrator and benefits 2.1 General Monostable (one-shot) or astable (free-running) operation True and complemented buffered outputs Only one external resistor and capacitor required NXP Semiconductors HEF4047B Monostable/astable multivibrator 2.2 Mono |
|