| No. | Partie # | Fabricant | Description | Fiche Technique |
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NXP |
Integrated silicon pressure sensor and benefits • 5.0% maximum error over 0° to 85° C • Ideally suited for microprocessor or microcontroller-based systems • Durable epoxy unibody and thermoplastic (PPS) surface mount package • Temperature compensated over –40° to +125° C • Patented si |
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NXP |
Integrated silicon pressure sensor and benefits • 5.0% maximum error over 0° to 85° C • Ideally suited for microprocessor or microcontroller-based systems • Durable epoxy unibody and thermoplastic (PPS) surface mount package • Temperature compensated over –40° to +125° C • Patented si |
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NXP |
Integrated silicon pressure sensor and benefits • 5.0% maximum error over 0° to 85° C • Ideally suited for microprocessor or microcontroller-based systems • Durable epoxy unibody and thermoplastic (PPS) surface mount package • Temperature compensated over –40° to +125° C • Patented si |
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NXP |
Integrated silicon pressure sensor and benefits • 5.0% maximum error over 0° to 85° C • Ideally suited for microprocessor or microcontroller-based systems • Durable epoxy unibody and thermoplastic (PPS) surface mount package • Temperature compensated over –40° to +125° C • Patented si |
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NXP |
Integrated silicon pressure sensor and benefits • 5.0% maximum error over 0° to 85° C • Ideally suited for microprocessor or microcontroller-based systems • Durable epoxy unibody and thermoplastic (PPS) surface mount package • Temperature compensated over –40° to +125° C • Patented si |
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NXP |
Integrated silicon pressure sensor and benefits • 5.0% maximum error over 0° to 85° C • Ideally suited for microprocessor or microcontroller-based systems • Durable epoxy unibody and thermoplastic (PPS) surface mount package • Temperature compensated over –40° to +125° C • Patented si |
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NXP |
Integrated silicon pressure sensor and benefits • 5.0% maximum error over 0° to 85° C • Ideally suited for microprocessor or microcontroller-based systems • Durable epoxy unibody and thermoplastic (PPS) surface mount package • Temperature compensated over –40° to +125° C • Patented si |
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NXP |
NPN general purpose transistor • Low current (max. 100 mA) • Low voltage (max. 45 V). APPLICATIONS • General purpose switching and amplification. DESCRIPTION NPN transistor in a TO-92; SOT54 plastic package. PNP complement: JA101. PINNING PIN 1 2 3 base collector emitter DESCRIPTI |
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NXP |
QorIQ integrated communication processor • Two e5500 Power Architecture cores (one on the P5010) – Each core has a backside 512-Kbyte L2 Cache with ECC – Three levels of instructions: User, Supervisor, and Hypervisor – Independent boot and reset – Secure boot capability • CoreNet fabric su |
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NXP |
8-Bit uP-compatible D/A Converter |
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NXP |
8-bit I2C and SMBus I/O port I 8 general purpose input/output expander/collector I Replacement for PCF8574 with integrated 2-kbit EEPROM I Internal 256 × 8 EEPROM I Self timed write cycle (5 ms typical) I 16 byte page write operation I I2C-bus and SMBus interface logic I Interna |
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NXP |
36-bit universal bus transceiver • 3-state non-inverting outputs for bus oriented applications • Wide supply voltage range of 1.2 to 3.6 V • Complies with JEDEC standard no. 8-1A • Current drive ±24 mA at 3.0 V • Universal bus transceiver with D-type latches and D-type flip-flops ca |
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NXP |
Integrated silicon pressure sensor and benefits • 5.0% maximum error over 0° to 85° C • Ideally suited for microprocessor or microcontroller-based systems • Durable epoxy unibody and thermoplastic (PPS) surface mount package • Temperature compensated over –40° to +125° C • Patented si |
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NXP |
Integrated silicon pressure sensor and benefits • 5.0% maximum error over 0° to 85° C • Ideally suited for microprocessor or microcontroller-based systems • Durable epoxy unibody and thermoplastic (PPS) surface mount package • Temperature compensated over –40° to +125° C • Patented si |
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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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NXP |
ultra small DC-to-DC buck converter and benefits Efficiency up to 95 % Extremely low output ripple in PWM and PFM mode 2 % total DC output voltage accuracy Soft start function for limiting inrush current Short circuit and over-temperature protection Enable input operates w |
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NXP |
18-bit universal bus transceiver • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latc |
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NXP |
2.5V/3.3V 18-bit universal bus transceiver • 18-bit bidirectional bus interface • 5V I/O Compatible • 3-State buffers • Output capability: +64mA/-32mA • TTL and LVTTL input and output switching levels • Bus-hold data inputs eliminate the need for external pull-up • Live insertion/extraction |
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NXP |
18-bit universal bus transceiver • 18-bit bidirectional bus interface • 3-State buffers • Output capability: +64mA/-32mA • TTL input and output switching levels • 74ABTH16501A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused i |
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NXP |
18-bit universal bus transceiver • 18-bit bidirectional bus interface • 3-State buffers • Output capability: +64mA/-32mA • TTL input and output switching levels • 74ABTH16501A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused i |
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