| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
Micron Technology |
GDDR5 SGRAM GDDR5 SGRAM MT51J256M32 – 16 Meg x 32 I/O x 16 banks, 32 Meg x 16 I/O x 16 banks Features • VDD = VDDQ = 1.5V ±3% and 1.35V ±3% • Data rate: 6.0 Gb/s, 7.0 Gb/s, 8.0 Gb/s • 16 internal banks • Four bank groups for tCCDL = 3 tCK • 8n-bit prefetch arch |
|
|
|
|
Micron Technology |
16K x 18 SRAM et4U.com et4U.com DataSheet4U.com DataShee DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com et4U.com DataSheet4U.com DataShee DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com et4U.com DataShee |
|
|
|
|
Micron Technology |
64K x 1 SRAM • High speed: 9, 10, 12, 15, 20 and 25ns • High-performance, low-power, CMOS double-metal process • Single +5V ±10% power supply • Easy memory expansion with /C/E option • All inputs and outputs are TTL-compatible 64K x 1 SRAM PIN ASSIGNMENT (Top Vi |
|
|
|
|
Micron Technology |
(MT58LxxxLxxD1) 4Mb SRAM |
|
|
|
|
Micron Technology |
(MT58LxxxLxxF1) 4Mb SRAM |
|
|
|
|
Micron Technology |
(MT58LxxxLxxF1) 4Mb SRAM |
|
|
|
|
Micron Technology |
(MT58LxxxLxxF1) 4Mb SRAM |
|
|
|
|
Micron Technology |
32K x 9 SRAM |
|
|
|
|
Micron Technology |
SRAM 2-WORD BURST • DLL circuitry for accurate output data placement MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B Figure 1 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE o |
|
|
|
|
Micron Technology |
1M SRAM |
|
|
|
|
Micron Technology |
(MT58xxxx) 16Mb SYNCBURST SRAM • Fast clock and OE# access times • Single +3.3V ±0.165Vor 2.5V ±0.125V power supply (VDD) • Separate +3.3V or 2.5V isolated output buffer supply (VDDQ) • SNOOZE MODE for reduced-power standby • Common data inputs and data outputs • Individual BYTE W |
|
|
|
|
Micron Technology |
(MT58xxxx) 16Mb SYNCBURST SRAM • Fast clock and OE# access times • Single +3.3V ±0.165Vor 2.5V ±0.125V power supply (VDD) • Separate +3.3V or 2.5V isolated output buffer supply (VDDQ) • SNOOZE MODE for reduced-power standby • Common data inputs and data outputs • Individual BYTE W |
|
|
|
|
Micron Technology |
(MT58xxxx) 16Mb SYNCBURST SRAM • Fast clock and OE# access times • Single +3.3V ±0.165Vor 2.5V ±0.125V power supply (VDD) • Separate +3.3V or 2.5V isolated output buffer supply (VDDQ) • SNOOZE MODE for reduced-power standby • Common data inputs and data outputs • Individual BYTE W |
|
|
|
|
Micron Technology |
(MT58xxxx) 16Mb SYNCBURST SRAM • Fast clock and OE# access times • Single +3.3V ±0.165Vor 2.5V ±0.125V power supply (VDD) • Separate +3.3V or 2.5V isolated output buffer supply (VDDQ) • SNOOZE MODE for reduced-power standby • Common data inputs and data outputs • Individual BYTE W |
|
|
|
|
Micron Technology |
(MT58LxxxLxxD1) 4Mb SRAM |
|
|
|
|
Micron Technology |
(MT58LxxxLxxD1) 4Mb SRAM |
|
|
|
|
Micron Technology |
(MT58LxxxLxxF1) 4Mb SRAM |
|
|
|
|
Micron Technology |
(MT58LxxxLxxF1) 4Mb SRAM |
|
|
|
|
Micron Technology |
(MT58LxxxLxxF1) 4Mb SRAM |
|
|
|
|
Micron Technology |
(MT55LxxxLxxF) 8Mb SRAM • • • • • • • • • • • • • • • • • • • • High frequency and 100 percent bus utilization Fast cycle times: 10ns, 11ns and 12ns Single +3.3V ±5% power supply (VDD) Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) Advanced control logic for m |
|