| No. | Partie # | Fabricant | Description | Fiche Technique |
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Lattice Semiconductor |
High-Speed Asynchronous E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 9 ns Maximum from Clock Input to Data Output — TTL Compatible 8 mA Outputs — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR |
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Lattice Semiconductor |
High Performance E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.0 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 75mA Typ Icc on Low Power D |
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Lattice Semiconductor |
Zero Power E2CMOS PLD • ZERO POWER E2CMOS TECHNOLOGY — 100µA Standby Current — Input Transition Detection on GAL16V8Z — Dedicated Power-down Pin on GAL16V8ZD — Input and Output Latching During Power Down • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 12 ns Maximum Propagation Del |
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Lattice Semiconductor |
Low Voltage E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • 3.3V LOW VOLTAGE 16V8 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Sta |
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Lattice Semiconductor |
Low Voltage E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology — TTL-Compatible Balanced 8mA Output Drive • 3.3V LOW VOLTAGE 20V8 ARCHITE |
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Lattice Semiconductor |
Low Voltage/ Zero Power E2CMOS PLD Generic Array Logic • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices — 50µA Typical Standby Current (100µA Max.) — 45mA Typical Active Current (55mA Max.) — Dedicated Power-down Pin • HIGH PERF |
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Lattice Semiconductor |
High Performance E2CMOS PLD |
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Lattice Semiconductor |
High Performance E2CMOS PLD Generic Array Logic Functional Block Diagram VccD I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I IISCALO I GND NC I I/O/Q I/O/Q I LNTDIENV I I/CLK NC Vcc I/O/Q I/O/Q • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 |
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Lattice Semiconductor |
High Performance E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 100 MHz — 6 ns Maximum from Clock Input to Data Output — TTL Compatible 12 mA Outputs — UltraMOS® Advanced CMOS Technology • 50% REDUCTION IN POWER FROM BIPOLAR — 75mA |
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Lattice Semiconductor |
High Performance E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 166 MHz — 4 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 75mA Typ Icc on Low Power Devic |
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Lattice Semiconductor |
High-Speed E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR |
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Lattice Semiconductor |
Low Voltage E2CMOS PLD Generic Array Logic Features • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 200 MHz — 3.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE — JEDEC-Compatible 3.3V Inte |
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Lattice Semiconductor |
High Performance E2CMOS PLD Generic Array Logic |
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Lattice Semiconductor |
High Performance E2CMOS PLD Generic Array Logic |
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Lattice Semiconductor |
Zero Power E2CMOS PLD • ZERO POWER E2CMOS TECHNOLOGY — 100µA Standby Current — Input Transition Detection on GAL16V8Z — Dedicated Power-down Pin on GAL16V8ZD — Input and Output Latching During Power Down • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 12 ns Maximum Propagation Del |
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Lattice Semiconductor |
High Performance E2CMOS FPLA Generic Array Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs — UltraMOS® Advanced CMOS Technology • LOW POWER CMOS — 90mA Typical Icc • E2 CELL TEC |
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Lattice Semiconductor |
High Performance E2CMOS FPLA Generic Array Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs — UltraMOS® Advanced CMOS Technology • ACTIVE PULL-UPS ON ALL PINS • LOW POWER CMOS — |
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Lattice Semiconductor |
High-Speed E2CMOS PLD Generic Array Logic • HIGH DRIVE E2CMOS® GAL® DEVICE — TTL Compatible 64 mA Output Drive — 15 ns Maximum Propagation Delay — Fmax = 80 MHz — 10 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • ENHANCED INPUT AND OUTPUT FEATURES — Schmitt |
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Lattice Semiconductor |
High Performance E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 111 MHz — 5.5 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs — UltraMOS® Advanced CMOS Technology • LOW POWER CMOS — 75 mA Typical Icc • ACTI |
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Lattice Semiconductor |
Zero Power E2CMOS PLD • ZERO POWER E2CMOS TECHNOLOGY — 100µA Standby Current — Input Transition Detection on GAL20V8Z — Dedicated Power-down Pin on GAL20V8ZD — Input and Output Latching During Power Down • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 12 ns Maximum Propagation Del |
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