| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
ICST |
Pentium/Pro System and Cyrix Clock Chip include four CPU, seven PCI and eight SDRAM clocks. Two reference outputs are available equal to the crystal frequency, plus the IOAPIC output powered by VDDL. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU |
|
|
|
|
ICST |
Clock Divider • Packaged as 8 pin SOIC • ICS’ lowest cost clock divider • Low skew (500ps) outputs. One is ÷ 2 of other. • Easy to use with other generators and buffers • Input clock frequency up to 156 MHz • Output clock duty cycle of 45/55 • Power Down turns off |
|
|
|
|
ICST |
LVPECL / ECL MULTIPLEXER • 1 differential 3.3V LVPECL output • 4:1 or 2:1 Crystal Oscillator Multiplexer • Supports parallel resonant crystals with a frequency range of 10MHz - 25MHz. The oscillator circuit is optimized for parallel resonant mode, and will require external c |
|
|
|
|
ICST |
LOW SKEW 1 TO 4 CLOCK BUFFER • • • • Outputs are skew matched to within 50ps Packaged in 16 pin TSSOP One PECL input to 4 PECL output clock drivers Operating Voltages of 3.3V to 5V Block Diagram VDD 62Ω 62Ω IN IN 270Ω Q0 270Ω Q0 VDD 62Ω 62Ω Q1 VDD 62Ω 62Ω 270Ω 270Ω Q1 Q2 |
|
|
|
|
ICST |
LVPECL/ECL FANOUT BUFFER • 6 differential LVPECL outputs • 1 differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: > 2GHz • Output skew: 30ps (maximum) • Part-to-part ske |
|
|
|
|
ICST |
LVPECL FANOUT BUFFER • 4 differential 3.3V LVPECL outputs • Selectable CLK or crystal inputs • CLK can accept the following input levels: LVCMOS, LVTTL • Maximum output frequency up to 266MHz • Output skew: 35ps (maximum) • Part-to-part skew: 150ps (maximum) • Propagatio |
|
|
|
|
ICST |
PRELIMINARY INFORMATION Clock Divider and 2X Multiplier • Packaged in 8 pin SOIC • Low cost clock divider and 2X multiplier • Low skew (500ps) outputs. One is ÷ 2 of other. • Easy to use with other generators and buffers • Input clock frequency up to 90 MHz at 5 V • Output clock duty cycle of 45/55 • Powe |
|
|
|
|
ICST |
Low Skew Clock Inverter and Divider • • • • • • Packaged in 16 pin narrow (150 mil) SOIC Input clock up to 160 MHz in the non-PLL mode Provides clock outputs of CLK, CLK, and CLK/2 Low skew (500 ps) on CLK, CLK, and CLK/2 All outputs can be tri-stated Entire chip can be powered down by |
|
|
|
|
ICST |
LVPECL/ECL FANOUT BUFFER • 2 differential 2.5V/3.3V LVPECL / ECL outputs • 1 differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 3GHz • Translates any single ended input signal |
|
|
|
|
ICST |
DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER • 5 differential LVPECL/ECL outputs • 2 selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: > 2GHz • Output skew: 13ps (typical) • P |
|
|
|
|
ICST |
LVPECL/ECL FANOUT BUFFER • (1) Differential 3.3V, 5V LVPECL / ECL output pair and (1) Single-ended 3.3V, 5V LVPECL / ECL output • (1) Differential D, nD input pair • D, nD pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: >3 |
|
|
|
|
ICST |
LVPECL/ECL FANOUT BUFFER • 9 differential 3.3V LVPECL / ECL outputs • 1 differential LVPECL input pair • PLCK, nPLCK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2GHz (typical) • Translates any single ended inp |
|
|
|
|
ICST |
DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER • Dual 2:1/1:2 MUX • 3 LVPECL outputs • 3 differential clock inputs • CLKx pair can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 3GHz • Part-to-part skew: 85ps (typical) • Additive jitter, RMS: 0.03ps |
|
|
|
|
ICST |
Quad Differential PCI-Express Clock Source • • • • • • • • • • • Packaged in 20-pin TSSOP Available in Pb (lead) free package Supports PCI-Express applications Four differential spread spectrum clock outputs Spread spectrum for EMI reduction Uses external 25 MHz clock or crystal input Power d |
|
|
|
|
ICST |
MP3 Audio Clock • Packaged in 16 pin TSSOP • Ideal for Cirrus Logic’s MP3 chips • Replaces multiple oscillators • 3.3V (will work down to 2.7V) or 5V operation • Uses an inexpensive 3.6864 MHz crystal or clock input • Supports 32 kHz, 44.1 kHz, 48 kHz, and 96 kHz au |
|
|
|
|
ICST |
Clock Synthesizer • • • • • • • • • • Extremely low operating current (11 mA) Packaged in 20-pin QFN (Pb-free) Input crystal or clock frequency of 27 MHz Output reference frequency of 27 MHz Fixed output frequencies of 37 MHz, 48 MHz and 22.5792 MHz Selectable output |
|
|
|
|
ICST |
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER • 2:1 LVPECL MUX • One LVPECL output • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 3GHz • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLK0, nPCLK0 • Pr |
|
|
|
|
ICST |
LVPECL/ECL RECEIVER • 4 differential LVPECL / ECL 1:1 receivers • 4 differential LVPECL clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: >2GHz (typical) • Translates any single ended |
|
|
|
|
ICST |
LVPECL MULTIPLEXER • 1 differential 2.5V, 3.3V or 5V LVPECL output • 2 selectable LVCMOS/LVTTL clock inputs • Output frequency: TBD • Additive phase jitter, RMS: 0.06ps (typical) • Propagation Delay: 370ps (typical) • 2.5V, 3.3V or 5V operating supply voltage (operatin |
|
|
|
|
ICST |
LVPECL/ECL CLOCK MULTIPLEXER • High speed 8:1 differential multiplexer • 1 differential 3.3V or 2.5V LVPECL output • 8 selectable differential PCLK, nPCLK inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output fr |
|