| No. | Partie # | Fabricant | Description | Fiche Technique |
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GSI Technology |
Rad-Tolerant SRAM • Aerospace-Level Product • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 2.5 V or 3.3 V +10%/ –10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mod |
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GSI Technology |
9Mb Sync Burst SRAMs Linear Burst Order (LBO) input. The Burst function need not • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation be used. New addresses can be loaded on every cycle with no degradation of chip per |
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GSI Technology |
(GS8161E18B - GS8161E36B) Sync Burst SRAMs • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/ –10% core power supply • 2.5 V or 3.3 V I/O supply www.DataSheet4U.com • LBO pin |
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GSI Technology |
9Mb Sync Burst SRAMs Linear Burst Order (LBO) input. The Burst function need not • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation be used. New addresses can be loaded on every cycle with no degradation of chip per |
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GSI Technology |
18Mb Sync Burst SRAMs • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • 2.5 V or 3.3 V +10%/ –10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors |
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GSI Technology |
18Mb Sync Burst SRAMs • IEEE 1149.1 JTAG-compatible Boundary Scan • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Byte Write (BW) and/or Global |
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GSI Technology |
(GS8161E18B - GS8161E36B) Sync Burst SRAMs • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/ –10% core power supply • 2.5 V or 3.3 V I/O supply www.DataSheet4U.com • LBO pin |
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GSI Technology |
(GS8161E18B - GS8161E36B) Sync Burst SRAMs • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/ –10% core power supply • 2.5 V or 3.3 V I/O supply www.DataSheet4U.com • LBO pin |
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GSI Technology |
Rad-Hard SRAM • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and pac |
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GSI Technology |
Rad-Hard SRAM • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and pac |
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GSI Technology |
Rad-Hard SRAM • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and pac |
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GSI Technology |
4Mb Sync Burst SRAMs • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10%/ –5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mod |
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GSI Technology |
144Mb SigmaQuad-II+ Burst of 4 SRAM • 2.5 Clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 4 Read and Write • On-Die Termination (ODT) on Data |
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GSI Technology |
36Mb Pipelined and Flow Through Synchronous NBT SRAM • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2.5 V or 3.3 V +10%/ –10% core power supply • 2.5 V or 3.3 V I/O supply |
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GSI Technology |
36Mb Sync Burst SRAMs • IEEE 1149.1 JTAG-compatible Boundary Scan • 1.8 V +10%/ –10% core power supply • 1.8 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Byte Write (BW) and/or Global Write ( |
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GSI Technology |
36Mb Pipelined and Flow Through Synchronous NBT SRAM • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2.5 V or 3.3 V +10%/ –10% core power supply • 2.5 V or 3.3 V I/O supply |
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GSI Technology |
36Mb Pipelined and Flow Through Synchronous NBT SRAM • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2.5 V or 3.3 V +10%/ –10% core power supply • 2.5 V or 3.3 V I/O supply |
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GSI Technology |
36Mb Pipelined and Flow Through Synchronous NBT SRAM • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2.5 V or 3.3 V +10%/ –10% core power supply • 2.5 V or 3.3 V I/O supply |
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GSI Technology |
Rad-Hard SRAM • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and pac |
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GSI Technology |
Rad-Hard SRAM • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and pac |
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