| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
Cypress Semiconductor |
128 Mbit (16 Mbyte) 3.0V SPI Flash Memory CMOS 3.0 Volt Core Density – 128 Mbits (16 Mbytes) Serial Peripheral Interface (SPI) with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Extended Addressing: 24- or 32-bit address options – Serial Command set and footprint compatible |
|
|
|
|
Cypress Semiconductor |
3.0V SPI Flash Memory Serial Peripheral Interface (SPI) with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Command subset and footprint compatible with S25FL-K Read – Normal Read (Serial): – 50 MHz clock rate (40 °C to +85 °C/105 °C) – Fast Read (Serial): |
|
|
|
|
Cypress Semiconductor |
3.0V SPI Flash Memory Serial Peripheral Interface (SPI) with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Command subset and footprint compatible with S25FL-K Read – Normal Read (Serial): – 50 MHz clock rate (40 °C to +85 °C/105 °C) – Fast Read (Serial): |
|
|
|
|
Cypress Semiconductor |
512 Mbit / 1.8 V Serial Peripheral Interface Serial Peripheral Interface (SPI) with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Double Data Rate (DDR) option – Extended Addressing – 24 or 32-bit address options – Serial Command subset and footprint compatible with S25FL-A, S25FL- |
|
|
|
|
Cypress Semiconductor |
Simultaneous Read/Write Flash Single 1.8 V read/program/erase (1.70 –1.95 V) 90 nm MirrorBit™ Technology Simultaneous Read/Write operation with zero latency Random page read access mode of 8 words with 20 ns intra page access time 32 Word / 64 Byte Write Buffer Sixteen |
|
|
|
|
Cypress Semiconductor |
3.0V SPI Flash Memory Serial Peripheral Interface (SPI) with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Command subset and footprint compatible with S25FL-K Read – Normal Read (Serial): – 50 MHz clock rate (40 °C to +85 °C/105 °C) – Fast Read (Serial): |
|
|
|
|
Cypress Semiconductor |
high-speed CMOS MirrorBit NOR flash devices ■ 3.0V I/O, 11 bus signals ❐ Single ended clock ■ 1.8V I/O, 12 bus signals ❐ Differential clock (CK, CK#) ■ Chip Select (CS#) ■ 8-bit data bus (DQ[7:0]) ■ Read-Write Data Strobe (RWDS) ❐ HyperFlash™ memories use RWDS only as a Read Data Strobe ■ Up t |
|
|
|
|
Cypress Semiconductor |
64 Mbit (8 Mbyte) 1.8-V FS-S Flash Serial Peripheral Interface (SPI) with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Double Data Rate (DDR) option – Extended Addressing - 24 or 32-bit address options – Serial Command subset and footprint compatible with S25FL1-K, S25FL |
|
|
|
|
Cypress Semiconductor |
SONET OC-48 Transceiver ■ SONET OC-48 operation ■ Bellcore and ITU jitter compliance ■ 2.488 GBaud serial signaling rate ■ Multiple selectable loopback or loop through modes ■ Single 155.52 MHz reference clock ■ Transmit FIFO for flexible data interface clocking ■ 16-bit pa |
|
|
|
|
Cypress Semiconductor |
Serial Peripheral Interface Density – S25FS128S-128 Mbits (16 Mbytes) – S25FS256S-256 Mbits (32 Mbytes) Serial Peripheral Interface (SPI) – SPI Clock polarity and phase modes 0 and 3 – Double Data Rate (DDR) option – Extended Addressing: 24- or 32-bit address options – Seri |
|
|
|
|
Cypress Semiconductor |
512 Mbit (64 Mbyte) 3.0V SPI Flash Memory CMOS 3.0 V Core with versatile I/O SPI with Multi-I/O Density ❐ 512 Mb (64 MB) SPI ❐ SPI Clock polarity and phase modes 0 and 3 ❐ DDR option ❐ Extended Addressing: 32-bit address ❐ Serial Command set and footprint compatible with S25FL-A, S2 |
|
|
|
|
Cypress Semiconductor |
128-Mbit 3.0 V Flash Memory |
|
|
|
|
Cypress Semiconductor |
128-Mb 3.0 V Flash Memory Memory Protection – WP#/ACC pin works in conjunction with Status Register Bits to protect specified memory areas – 256 KB uniform sector product: Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as |
|
|
|
|
Cypress Semiconductor |
Serial Peripheral Interface Density – S25FS128S-128 Mbits (16 Mbytes) – S25FS256S-256 Mbits (32 Mbytes) Serial Peripheral Interface (SPI) – SPI Clock polarity and phase modes 0 and 3 – Double Data Rate (DDR) option – Extended Addressing: 24- or 32-bit address options – Seri |
|