The ZL30414 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30414 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC3 rates and ITU-T G.8.
• Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates Provides four LVPECL differential output clocks at 622.08 MHz Provides a CML differential clock at 155.52 MHz Provides a single-ended CMOS clock at 19.44 MHz Lock Indicator Provides enable/disable control of output clocks Accepts a CMOS reference at 19.44 MHz 3.3 V supply Ordering Information ZL30414QGC 64 Pin TQFP Trays ZL30414QGC1 64 Pin TQFP
* Trays
*Pb Free Matte Tin -40° C to +85 ° C
February 2005
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De.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | ZL30410 |
Zarlink Semiconductor |
Multi-service Line Card PLL | |
2 | ZL30415 |
Zarlink Semiconductor |
SONET/SDH Clock Multiplier PLL | |
3 | ZL30416 |
Zarlink Semiconductor |
SONET/SDH Clock Multiplier PLL | |
4 | ZL30402 |
Zarlink Semiconductor Inc |
SONET/SDH Network Element PLL | |
5 | ZL30406 |
Zarlink |
SONET/SDH Clock Multiplier PLL | |
6 | ZL30407 |
Zarlink Semiconductor Inc |
SONET/SDH Network Element PLL | |
7 | ZL30409 |
Zarlink Semiconductor Inc |
T1/E1 System Synchronizer with Stratum 3 Holdover | |
8 | ZL30100 |
Zarlink Semiconductor Inc |
T1/E1 System Synchronizer | |
9 | ZL30101 |
Zarlink Semiconductor Inc |
T1/E1 Stratum 3 System Synchronizer | |
10 | ZL30102 |
Zarlink Semiconductor |
T1/E1 Stratum 4/4E Redundant System Clock Synchronizer | |
11 | ZL30105 |
Zarlink Semiconductor |
T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer | |
12 | ZL30106 |
Zarlink |
SONET/SDH/PDH Network Interface DPLL |