WS512K32V-XXX - ETC

WS512K32V-XXX 512Kx32 SRAM 3.3V MODULE

I/O0-31 A0-18 WE1-4 CS1-4 I/O29 I/O28 A0 A1 A2 WE1 CS 1 Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected OE VCC GND NC BLOCK DIAGRAM WE2 CS2 WE3 CS 3 WE 4CS4 OE A0-18 512K x 8 512K x 8 I/O23 I/O22 512K x 8 512K x 8 I/O21 I/O20 66 I/O0-7 I/O8-15 I/O16-23 I/O24-31 8 8 8 8 May 2001 Rev. 6 1 .

Features

s Access Times of 15, 17, 20ns s Low Voltage Operation s Packaging
• 66-pin, PGA Type, 1.075 inch square, Hermetic Ceramic HIP (Package 400)
• 68 lead, 22.4mm (0.88") CQFP, 4.6mm (0.180") high, (Package 509) PRELIMINARY
* s Low Power CMOS s TTL Compatible Inputs and Outputs s Fully Static Operation:
• No clock or refresh required. s Three State Output. s Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation s Weight WS512K32V-XG2TX - 8 grams typical WS512K32V-XG1UX - 5 grams typical WS512K32NV-XH1X - 13 grams typical
* This data sheet describes a product under development,.