W83627DHG - Winbond

W83627DHG LPC I/O

Date : April 10, 2007 Version : 1.4 W83627DHG Data Sheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS 1 2 N.A. N.A. 12/15/2005 02/22/2006 0.1 0.2 N.A. N.A. 1. 1. 1. 2. 3. 4. 5. 6. 7. 1. 2. 3. 4. First published version. Add descriptions of the registers, functions,, AC/DC timing, and top marking Revise Table 8.1 and the timing ch.

Features

Add descriptions of PECI and SST and a table of SMBus in Chapter 5 Pin Description. Add new sections of Caseopen and Beep Alarm Function in Chapter 7 Hardware Monitor. Add Clock Input Timing, PECI & SST Timing, and SPI Timing in Chapter 21 Specifications. Remove sections 9.4 and 9.5 (EXTFDD and EXT2FDD). Modify the descriptions of Hardware Monitor Device, Bank 0, Index 59h, bits(6..4). Add a beep control bit for VIN4 at Hardware Monitor Device, Bank 0, Index 57h, bit6. Remove status bit of PME# status of MIDI IRQ event at Logical Device A, CRF4, bit 1. Remove control bit of enable/disable PME.