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W83627DHG |
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| Part Number | W83627DHG |
| Manufacturer | Winbond |
| Description | Date : April 10, 2007 Version : 1.4 W83627DHG Data Sheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS 1 2 N.A. N.A. 12/15/2005 02/22/2006 0.1 0.2 N.A. N.A. 1. 1. 1. 2. 3. 4... |
| Features |
Add descriptions of PECI and SST and a table of SMBus in Chapter 5 Pin Description. Add new sections of Caseopen and Beep Alarm Function in Chapter 7 Hardware Monitor. Add Clock Input Timing, PECI & SST Timing, and SPI Timing in Chapter 21 Specifications. Remove sections 9.4 and 9.5 (EXTFDD and EXT2FDD). Modify the descriptions of Hardware Monitor Device, Bank 0, Index 59h, bits(6..4). Add a beep control bit for VIN4 at Hardware Monitor Device, Bank 0, Index 57h, bit6. Remove status bit of PME# status of MIDI IRQ event at Logical Device A, CRF4, bit 1. Remove control bit of enable/disable PME... |
| Document |
 W83627DHG Data Sheet
PDF 1.93MB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | W83627DHG-P |
nuvoton |
LPC I/O |
|
| 2 | W83627DHG-PT |
nuvoton |
LPC I/O |
|
| 3 | W83627EHF |
Winbond Electronics |
LPC I/O |
|
| 4 | W83627EHF-EF |
Winbond |
LPC I/O |
|
| 5 | W83627EHG |
Winbond Electronics |
LPC I/O |
|