W13NB60 - STMicroelectronics

W13NB60 STW13NB60

Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charg.

Features

DM (
• ) P tot dv/dt( 1 ) V ISO Ts tg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω ) G ate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 oC Drain Current (pulsed) T otal Dissipation at Tc = 25 C Derating Factor Peak Diode Recovery voltage slope Insulation W ithstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature o o TO-247 ISOWATT218 INTERNAL SCHEMATIC DIAGRAM Value STW 13NB60 STH13NB60FP 600 600 ± 30 13 8.2 52 190 1.52 4  -65 to 150 150 ( 1) ISD ≤ 13 A, di/dt ≤ 200 Α/µs, VDD ≤ V(BR)D.