UPD30121 - NEC

UPD30121 64-/32-BIT MICROPROCESSOR

are provided in the following user’s manual. Be sure to read it before designing. • VR4121 User’s Manual (U13569E) DESCRIPTION FEATURES • Employs 64-bit MIPS architecture • Conforms to MIPS III instruction set (deleting FPU, LL, LLD, SC, and SCD instructions) • Optimized 6-stage pipeline • Supports MIPS16 instruction set • Supports high-speed product-sum .

Features

• Employs 64-bit MIPS architecture
• Conforms to MIPS III instruction set (deleting FPU, LL, LLD, SC, and SCD instructions)
• Optimized 6-stage pipeline
• Supports MIPS16 instruction set
• Supports high-speed product-sum operation instructions
• Supports four types of operating modes, enabling more effective power-consumption management
• Internal maximum operating frequency: 131/168 MHz
• On-chip clock generator
• Address space physical: 32 bits virtual: 40 bits Integrates 32 double entry TLBs
• High-capacity instruction/data separated cache memories Instruction: 16 Kbytes Data: 8 Kbytes
• Me.