TPIC6259 - Texas Instruments

TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH

DRAIN3 7 S1 8 14 DRAIN4 13 G This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is LGND 9 PGND 10 12 S2 11 PGND designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multifunctional device ca.

Features

HER DRAIN Qio Qio FUNCTION Addressable Latch decoding or demultiplexing mode active-low DMOS outputs. Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs H HX Qio L LH L L LL H L HX H Qio Memory H 8-Line H Demultiplexer H Clear as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) LATCH SELECTION TABLE terminal is written into the addressed latch. The addressed DMOS transistor output inverts the SELECT INPUTS DRAIN S2 S1 S0 ADDRESSED data input with all unaddressed DMOS-transistor ou.