TC35274 - Toshiba Semiconductor

TC35274 TOSHIBA MPEG-4 Video Decoder LSI

System Reset Input (Low Active). When the LSI is reset, this terminal has to be low for more than 16 clock cycles. When power on, the LSI has to be reset after PLL locked. It takes approximately 100us until the PLL locked. System Standby Input (High Active). Stop clock distribution to the LSI. After standby, system reset is required. “0” : Active. “1” : Stan.

Features

U A single-chip MPEG-4 video decoder LSI performs 15frames/sec of MPEG-4 video decoding with QCIF (176x144 pixels) at 30MHz clock frequency. U A 4-Mbit embedded DRAM is integrated to reduce power consumption without performance degradation. U An MPEG-4 video core consists of a 16-bit RISC processor and dedicated hardware accelerators so as to bring programmability, high performance, and low power consumption. P-FBGAxxxx U Firmware program for the RISC is downloaded into the embedded DRAM before starting operation. Other applications, such as H.263, are performed by using appropriate fi.