TC35273 - Toshiba Semiconductor

TC35273 MPEG-4 Audiovisual LSI

System Reset Input (Low Active). When the LSI is reset, the reset pin has to be low for more than 16 clock cycles. When power on, the LSI has to be reset after PLL locked. It takes approximately 100us until the PLL locked. System Standby Input (High Active). When it is high, power is not supplied to the internal logic, SRAM, and DRAM. “0”: Normal Operation. .

Features

www.DataSheet4U.com U TC35273 is an MPEG-4 audiovisual codec LSI which supports 3GPP 3G-324M video telephony system. MPEG-4 video codec with QCIF (176x144 pixel) at 15 frames/s, AMR (Adaptive Multi Rate) speech codec, and ITU-T H.223 are executed concurrently at around 70MHz clock rate. U Three signal processing units, an MPEG-4 video codec, a speech codec / audio decoder, and a multiplex / demultiplex unit, are integrated on a single chip. P-FBGA201-1515-0.80A5 U A 12-Mbit embedded DRAM is integrated as a shared memory for the three signal processing units. The embedded DRAM helps to re.