SUD50N06-08H - Vishay Siliconix

SUD50N06-08H P-Channel MOSFET

The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacita.

Features

ation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73185 20-Oct-04 www.vishay.com 1 SPICE Device Model SUD50N06-08H Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 3.5 662 0.0064 0.0096 0.0114 0.91 Measured Data Unit VGS(th) ID(on) .