ordering information The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outp.
These versatile flip-flops perform as toggle flip-flops by tying J and K high. SN54HC112 . . . J OR W PACKAGE SN74HC112 . . . D OR N PACKAGE (TOP VIEW) 1CLK 1 1K 2 1J 3 1PRE 4 1Q 5 1Q 6 2Q 7 GND 8 16 VCC 15 1CLR 14 2CLR 13 2CLK 12 2K 11 2J 10 2PRE 9 2Q SN54HC112 . . . FK PACKAGE (TOP VIEW) 1K 1CLK NC VCC 1CLR 1J 1PRE NC 1Q 1Q 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2CLR 2CLK NC 2K 2J 2Q GND NC 2Q 2PRE NC − No internal connection ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC112N SN74HC112N −40°C to 8.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | SNJ54HC112FK |
Texas Instruments |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS | |
2 | SNJ54HC112J |
Texas Instruments |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS | |
3 | SNJ54HC109FK |
Texas Instruments |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS | |
4 | SNJ54HC109J |
Texas Instruments |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS | |
5 | SNJ54HC109W |
Texas Instruments |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS | |
6 | SNJ54HC10FK |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATES | |
7 | SNJ54HC10J |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATES | |
8 | SNJ54HC10W |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATES | |
9 | SNJ54HC148FK |
Texas Instruments |
8-LINE TO 3-LINE PRIORITY ENCODERS | |
10 | SNJ54HC148J |
Texas Instruments |
8-LINE TO 3-LINE PRIORITY ENCODERS | |
11 | SNJ54HC148W |
Texas Instruments |
8-LINE TO 3-LINE PRIORITY ENCODERS | |
12 | SNJ54HC14J |
Texas Instruments |
Hex Schmitt-Trigger Inverters |