SN74HC109N - Texas Instruments

SN74HC109N DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

These devices contain two independent J-K positiveedge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going .

Features

• Wide operating voltage range of 2 V to 6 V
• Low input current of 1 μA max
• High-current outputs drive up to 10 LSTTL loads
• Low power consumption, 40-μA max ICC
• Typical tpd = 12 ns
• ±4-mA output drive at 5 V 2 Description These devices contain two independent J-K positiveedge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of t.