SN54LS195A - Motorola Inc

SN54LS195A UNIVERSAL 4-BIT SHIFT REGISTER

The Logic Diagram and Truth Table indicate the functional characteristics of the LS195A 4-Bit Shift Register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The LS195A has two primary modes of operation, shift ri.

Features

25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 1 D SUFFIX SOIC CASE 751B-03 PE P0
  – P3 J K CP MR Q0
  – Q3 Q3 Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage J (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs (Note b) Complementary Last Stage Output (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 9 4 5 6 7 NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Outpu.