SN54LS165 - Motorola Inc

SN54LS165 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER

The SN54/74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL signal is LOW. The parallel data can change while PL is LOW, provided that the recommended setup and hold times are observed. For clock operation, PL must b.

Features

W) Input Parallel Data Inputs Serial Output from Last State (Note b) Complementary Output (Note b) LOADING (Note a) HIGH 0.5 U.L. 0.5 U.L. 1.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.75 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. TRUTH TABLE CP PL 1 L H H H H X L H 2 X Q0 P0 DS Q0 DS Q0 Q1 P1 Q0 Q1 Q0 Q1.