SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL .
– 0.4
–100 1.2 3.3 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5
– 0.65 3.5 0.8
– 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN =
– 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERIS.
SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVIS.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | SN54LS107A |
Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | |
2 | SN54LS107A |
Texas Instruments |
DUAL J-K FLIP-FLOPS | |
3 | SN54LS109A |
Motorola Inc |
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP | |
4 | SN54LS109A |
Texas Instruments |
Dual J-K Positive-Edge-Triggered Flip-Flops | |
5 | SN54LS11 |
Motorola Inc |
TRIPLE 3-INPUT AND GATE | |
6 | SN54LS11 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-AND GATES | |
7 | SN54LS112A |
Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | |
8 | SN54LS112A |
Texas Instruments |
Dual J-K Negative-Edge-Triggered Flip-Flops | |
9 | SN54LS113A |
Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | |
10 | SN54LS114A |
Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | |
11 | SN54LS12 |
Motorola Inc |
TRIPLE 3-INPUT NAND GATE | |
12 | SN54LS12 |
Texas Instruments |
POSITIVE-NAND GATE |