SI53115 - Silicon Laboratories

SI53115 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

The Si53115 is a 15-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/ Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applicati.

Features

 Fifteen 0.7 V low-power, push-
 Separate VDDIO for outputs pull HCSL PCIe Gen3 outputs
 PLL or bypass mode
 100 MHz /133 MHz PLL
 Spread spectrum tolerable
 operation, supports PCIe and QPI
 PLL bandwidth SW SMBUS programming overrides the latch

 1.05 to 3.3 V I/O supply voltage 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) value from HW pin
 Low phase jitter (Intel QPI, PCIe
 9 selectable SMBUS addresses Gen 1/2/3/4 common clock compliant)
 SMBus address configurable to allow multiple buffers in a single
 Gen 3 SRNS Compliant control network 3.3.