SI53112 - Silicon Laboratories

SI53112 DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

The Si53112 is a low-power, 12-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. .

Features

 Twelve 0.7 V low-power, push-
 PLL or bypass mode pull, HCSL-compatible
 Spread spectrum tolerable PCIe Gen 3 outputs
 1.05 to 3.3 V I/O supply voltage
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 Individual OE HW pins for each output clock 100 MHz /133 MHz PLL operation, supports PCIe and QPI
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 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) Low phase jitter (Intel QPI, PCIe Gen 1/2/3/4 common clock compliant)
 PLL bandwidth SW SMBUS programming overrides the latch
 Gen 3 SRNS Compliant value from HW pin
 100 ps input-to-output delay
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 9 selectable SMBUS addresses SMBus address configurable.