Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit and 4-bit read/write and test are possible. Individual pins are software configurable as input or output; Individual pins are software configurable as open-drain or push-pull output; Individual pull-up resistors are software assignable; pull-up resistors are automatically disabled f.
Memory
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• 512 × 4-bit RAM (including LCD display RAM) 8,192 × 8-bit ROM Interrupts
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• Four internal vectored interrupts Five external vectored interrupts Two quasi-interrupts
28 I/O Pins
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• I/O: 26 pins (44-pin QFP, 42-pin SDIP) Output only: 2 pins (44-pin QFP)
Bit Sequential Carrier
• Supports 16-bit serial data transfer in arbitrary format
LCD Controller/Driver
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• 12 segments and 8 common terminals (3, 4, and 8 common selectable) Internal resistor circuit for LCD bias All dot can be switched on/off Memory-Mapped I/O Structure
• Data memory bank 15
Power-Down Modes
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• Idle mode.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | S3P7235 |
Samsung semiconductor |
The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrange | |
2 | S3P7238 |
Samsung semiconductor |
The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrange | |
3 | S3P7295 |
Samsung semiconductor |
The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M | |
4 | S3P72B9 |
Samsung semiconductor |
The S3C72B5/C72B7/C72B9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung A | |
5 | S3P72E8 |
Samsung semiconductor |
The S3C72E8/P72E8 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and LCD drivers. | |
6 | S3P72F5 |
Samsung semiconductor |
The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M | |
7 | S3P72G9 |
Samsung semiconductor |
The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M | |
8 | S3P72G9 |
Samsung semiconductor |
SAM47 INSTRUCTION SET | |
9 | S3P72H8 |
Samsung semiconductor |
The S3C72H8 single-chip CMOS microcontroller has been designed for very high performance using Samsungs state-of-the-art 4-bit product development app | |
10 | S3P72I9 |
Samsung semiconductor |
The S3C72I9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M | |
11 | S3P72K8 |
Samsung semiconductor |
singl-chip CMOS microcontroller | |
12 | S3P72N4 |
Samsung semiconductor |
The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrange |