S26KS128S - Cypress Semiconductor

S26KS128S high-speed CMOS MirrorBit NOR flash devices

...... 4 1.1 DDR Center Aligned Read Strobe Functionality (DCARS) .... 6 1.2 Error Detection and Correction Functionality. 6 2. Connection Diagram...... 9 2.1 FBGA 24-Ball 5 x 5 Array Footprint ..

Features

■ 3.0V I/O, 11 bus signals
❐ Single ended clock
■ 1.8V I/O, 12 bus signals
❐ Differential clock (CK, CK#)
■ Chip Select (CS#)
■ 8-bit data bus (DQ[7:0])
■ Read-Write Data Strobe (RWDS)
❐ HyperFlash™ memories use RWDS only as a Read Data Strobe
■ Up to 333 MBps sustained read throughput
■ DDR
  – two data transfers per clock
■ 166-MHz clock rate (333 MBps) at 1.8V VCC
■ 100-MHz clock rate (200 MBps) at 3.0V VCC
■ 96-ns initial random read access time
❐ Initial random access read latency: 5 to 16 clock cycles
■ Sequential burst transactions
■ Configurable Burst Characteristics
❐ Wrapped burst leng.