Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 .
■ 32-bit RX CPU core
Max. operating frequency: 32 MHz
Capable of 49 DMIPS in operation at 32 MHz
Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
■ Low-power design and architecture
Operation from a single 1.62-V to 5.5-V supply
1.62-V operation available (at up to TBD MHz)
Thr.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | R5F52203BDFK |
Renesas |
32-MHz 32-bit RX MCUs | |
2 | R5F52203BDFM |
Renesas |
32-MHz 32-bit RX MCUs | |
3 | R5F52203BDFP |
Renesas |
32-MHz 32-bit RX MCUs | |
4 | R5F52203BGFK |
Renesas |
32-MHz 32-bit RX MCUs | |
5 | R5F52203BGFL |
Renesas |
32-MHz 32-bit RX MCUs | |
6 | R5F52203BGFM |
Renesas |
32-MHz 32-bit RX MCUs | |
7 | R5F52203BGFP |
Renesas |
32-MHz 32-bit RX MCUs | |
8 | R5F52201BDFK |
Renesas |
32-MHz 32-bit RX MCUs | |
9 | R5F52201BDFL |
Renesas |
32-MHz 32-bit RX MCUs | |
10 | R5F52201BDFM |
Renesas |
32-MHz 32-bit RX MCUs | |
11 | R5F52201BGFK |
Renesas |
32-MHz 32-bit RX MCUs | |
12 | R5F52201BGFL |
Renesas |
32-MHz 32-bit RX MCUs |